Proposed Modifications to Prototype SVT Data Transmission Electronics for Noise Testing at UC Santa Barbara 6/11/97 Max Wilder At the present time, we know only that the printed circuit board version of the prototype electronics is too noisy. We do not know what the noise generator is, what path the noise follows, or what part of the ATOM chip is sensitive to the noise. We propose a new series of noise tests to take place at UCSB, with modified electronics, to throw some light on these matters. It is probable that the noise is being coupled directly into the front end of the ATOM chip. A second possible point of entry is at the signal transfer between the analog amplifier and the digital comparator in the ATOM chip, however Issy Kipness had simulated the circuit at this point and assures us that it is noise resistant. The noise is likely to appear as a fluctuation between the analog 2V supply and another analog supply, or the shield. HDI Link Card #3 Card #3 will have minimum modifications and will function as a benchmark for noise testing. It will also be used to test the effect of better bypassing of the cable driver/receiver electronics, which is the prime suspect for a noise generator. 1) The digital section to be loaded normally (i.e. according to schematic), with the addition of 47uF bypassing caps between all D5x_Local and D0x_Local supplies for cable driver/receiver circuitry. These should have been put in the original design. In addition, the D5x_Local and D0x_Local power traces running between the power connectors and the digital section of the board should be cut and jumpered, so that the digital sections can be powered through the power connector, or via a separate twisted pair power cable. The reason for this modification is that the digital power supply traces run both above and below the analog power traces, allowing digital noise to couple into the analog power. As part of this test we will compare noise levels with and without bypassing between System_5V and D5x_Local by removing those coupling caps in situ. We expect that the noise level will be much less sensitive to the presence or absence of those caps if the D5x_Local supply is well bypassed to D0x_Local. 2) the analog sections will be loaded as follows: channel 1(defined as the section at the top edge of the board): to be loaded the same as schematic, including bypassing caps between n- and p-side analog supplies. bypassing caps between A2x and shield are not to be loaded since they were not loaded on Cards #1 and #2. channel 2: each supply to be bypassed to it’s own current return only. There will be no bypassing caps between n- and p-side analog supplies, or between A2x and shield. HDI Link Card #4 Card #4 will be configured with as many bypassing, grounding, and shielding options as possible, to locate the primary noise source on the board, and the propagation path. The board must be configured so that we can test one modification at a time. 1) The digital power and bypassing will be done as on Card #3. 2) the analog bypassing will be done as in Card #3, channel 2. That is, there will be no bypassing between p- and n-sides, or to shield layer. Extra bypassing caps should be taken so that this bypassing can be added if it improves noise perfomance. 2) The signal and power cable connectors will be isolated from the shield layer by drilling out vias for shield pins, and isolating connector mounting hardware from the square pads connected to shield layer. The isolation will be done in such a way that the cable shields can be connected to the shield layer, or jumpered together with metal braid thus avoiding the shield layer completely. The connector shield pins should be soldered together and have the same connection options as the cable shield, or be left floating. 3) The System_Gnd and shield layers (layers 6 and 7) on the channel 1 power section will be isolated by milling a slot through these layers, between channels 1 and 2 across the entire board. A fiberglass stiffener will be added to prevent the board from bending at the slot. The Channel 1 ground and shield layers are always isolated from the digital section. The ground layer is always floating. The shield layer can be configured in the following ways: a) shield layer floating or grounded, cable shields isolated from shield layer and jumpered together with braid. b) shield layer connected to cable shields. In both cases the noise path from digital electronics to shield layer to analog power bus is eliminated. In both cases, there is a possible noise path via capacitive coupling between analog power traces and the underlying ground plane. This path cannot be eliminated except by using a separate prototype analog section with no ground or shield plane (e.g. vector board with power connectors, bypass caps, and pin-to-pin wiring between connectors). Channel 2 always shares the ground and shield layers with the digital section. Channel 2 can be configured in the following ways: a) cable shields connected to shield layer as on Card #3. b) cable shields jumpered togther and isolated from shield layer. Shield layer floating or grounded. This tests two noise paths: a) from digital electronics to shield layer, from shield layer to analog power traces. From analog traces to front-end electronics? If both analog power supplies and shield are bouncing together, why should the front-end electronics care? b) from digital electronics to shield layer, from shield layer to cable shield, from cable shield to twisted pairs in cables or to front end electronics via shield bypassing caps. Again, if the same noise gets on to shield and analog power, what is the problem? The signal cable shield provides a distinct noise path. Noise could exist as a common mode fluctuation on the signal lines with respect to the shield. Or low impedance foreward and back termination on signal lines may provide noise path from digital Vdd on HDI Link Card to digital Vdd on HDI Detector Module with respect to the shield.