The following plot shows the relation between the internal and the external duty cycle. The external width was measured at the input of the chips. The internal width was measured after the receivers on the pads clk_ap and clk_am. The measurements were done for radhard chips (board 6, no Irr).
The rise time (10 - 90%) of the leading and falling edge of clk_ap is 1.5 ns and 1.2 ns respectively.
Last Updated on 6/7/97
By Wilko