Irradiation Tests

A test board with three AToM chips, rad-hard version 2, was irradiated with Co-60. The total dose was 1.07 Mrad and was accumulated in two steps. In the first steps the dose was 260 Krad.
The dose rate was 9 Krad per hour. The results that are presented here are those after the full dose, 1.07 Mrad.

Summary

The effect of the irradiation on the duty cycle was similar to the one observed with the rad-hard version 1. Typically the workable duty cycle range narrows down by a few percent. The write register command, which has the smallest duty cycle range, does not working anymore at 60 MHz. It starts to operate at about 55 MHz.

The biggest problems and oddities are observed in the token passing. In particular the duty cycle range for the token passing and for the readout sequence do not overlap very well. At 60 MHz the range where both commands are working well is only a few percent.

Write Control Register

The following two figures compare the duty cycle range for the write register command before and after irradiation. The range decreased by about 4 % - 5% after 1.07 Mrad irradiation. At 60 MHz the write register command is not working anymore at all.

Global Commands

Readout Sequence

A readout sequence consists of: test pattern inject -> trigger accept -> readout The duty cycle range changes only very little after the irradiation. The following figures compares the ranges before and after irradiation for two chips.

Token Passing

The strangest results are obtained from token passing tests. The test consists of two steps:

The registers of the three chips are written, at a low frequency (25 - 30 MHz). The masks are written so that all channels are disabled.
A readout sequence (trigger accept followed by a readout command) are issued. The frequency is changed slowly (turning a dial) or abrupt (programing the value and hiting the enter-button).

Because there are no data in the pipeline the token passing output consists just of the data headers of the chips separated by 16 zeros. The followig was observed.

The clock period was fixed. And the duty cycle was changed from high values to low values. The token passing worked all the way down. However if the duty cycle was changed from low values to high values, there was a duty cycle where all three chips got reset. The register content then read is the one after a chip reset command or after power on.
For very low values of the duty cycle the chips put out random data and the rate of data increases with decreasing duty cycle. All three chips showed this behaviour, but the middle chip more strongly than the other two.
The extra data typically have time-stamps of zero, and the address are random. The tot is most often 15, but other values also show up.

The following figure shows the duty cycle range for the token passing and a readout sequence (with an injected testpattern) for an individual chip. The plots shown are after the irradiation.
The lower range for the token passing is significantly higher than that for a readout sequence. The overlap range between both commands (low range curve from token passing and high range curve from readout sequence) is very small at 60 MHz, about 3 %. At 30 MHz the range is about 50 %.