GTRC_b and GTFE64_c Commands and Configuration

Introduction

This page address the commands for the GTRC version B and the front-end chip GTFE64 version C. It also describes the configuration of the chips register.

Index

Controller Commands
GTFE Commands
GTFE Register
GTRC output data format
Description of Commands
1. Reset Signal
2. Write GTRC Register

Controller Commands

A controller (GTRC) command has the following format:

Start bit: 1.
GTRC Address : 5 bits, LSB last, Wild-card address 11111 addresses all chips simultaneously.
Command: 3 bits, LSB last.
Data: data length depends on the command.

N_i: controller chip address.
M_i: front-end chip (GTFE) address.

Load GTRC	1 N_4-0 000	Data(8 bits)
Clear Event	1 N_4-0 001
Read Event	1 N_4-0 010
Load GTFE Reg.	1 N_4-0 011	1 100 M_0-4 DATA(207)
Turn On Clock	1 N_4-0 100
Calib strobe	1 N_4-0 101	1 110 M_0-4
Reset GTFE	1 N_4-0 110	1 101 M_0-4
Reset GTFE FiFo	1 N_4-0 110	1 011 M_0-4
Reset GTRC	1 N_4-0 111

GTFE Commands

GTFE Commands (start bit omitted)
Name	command address cmd_0-2 M_0-4
No-Op	000 M_0-4
Load register	100 M_0-4
Read-Event	010 M_0-4
Calib-Strobe	110 M_0-4
Clear-Event	001 M_0-4
Reset Gtfe	101 M_0-4
Reset Fifo	011 M_0-4
End Read-Event	111 M_0-4

Reset Signal

The reset signal is a single ended signal that if in the high state resets the controller and front end chip.

Controller: The default register values are loaded.

GTFE: The register is not reset but the content is preserved.

Write GTRC register

The GTRC register consists of 8 bits. Bit 0 is sent first. If the register is written the previous content of the register is shifted out and appears at the data output of the controller chip. The default bit pattern is 11100101 (bit0 - bit7). The default pattern is loaded if a reset signal is received but not changed by a reset_GTRC command.

Control Register GTRC version a
bit content default

0 not used 1

1 Read out the layer even if it didn't generated a fast-or 1=default=no

2 Calculate and include 11bit check sum 1=default=yes

3-7 Number of chips to read. bit3=MSB, bit7=LSB default = 5

Control Register GTRC version a
bit	content	default
0	not used	1
1	Read out the layer even if it didn't generated a fast-or	1=default=no
2	Calculate and include 11bit check sum	1=default=yes
3-7	Number of chips to read. bit3=MSB, bit7=LSB	default = 5

Reset GTRC

The reset-GTRC command resets the controller but doesn't change the register content.

Reset GTFE

The reset-GTFE command resets the fond-end chip. The default register settings are loaded.

Reset GTFE

The reset-GTFE-FiFo command resets the GTFE Fifo buffer pointer.

Write GTFE Register

The gtfe register consists of 207 bits. Bit 0 is send first. The default settings are loaded by a reset_GTFE command, but not changed by the reset pulse (For the controller chips it is the other way round).

GTFE register
Bits Entry

0 - 63 calib mask (0-63)

64 - 127 chan mask (63-0)

128 - 191 fastOr mask (0-63)

192 calDac range

193 - 198 calDac (193 MSB)

199 thresDac range

200 - 205 thresDac (200: MSB)

206 direction

GTFE register
Bits	Entry
0 - 63	calib mask (0-63)
64 - 127	chan mask (63-0)
128 - 191	fastOr mask (0-63)
192	calDac range
193 - 198	calDac (193 MSB)
199	thresDac range
200 - 205	thresDac (200: MSB)
206	direction

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Last modified: Fri Oct 20 10:29:59 PDT 2000