Return GTFE64   Return GLAST
GTFE64 Commands and Register

Commands

Commands for the GTFE64 version D and higher. The commands described here are the one that are sent directly to the GTFE without using the controller chip.

A command consist of a 11 bit header followed by an optional data format. The first bit is the start bit. It is followed by five bits for the GTFE address with the MSB right after the start bit. The address bit is followed by the command code. The first bit of the comand code is the MSB.

The data depends on the command. There are three different formats: 1) no data at all, 2) default data which are 68 bits long and 3) a special format for the read-event command, which has only two bits.

cmd bits comments
no-op 1 aaaaa 00000 no operation
Reset Chip 1 aaaaa 00010 reset chip, no data
read-event Sequence 1 aaaaa 00100 B1B0 Start readout sequence. B1 and B0 are the two bits that specify one of the four event registers to be output.
Load GTFE data mask 1 aaaaa 01000 data  
Load GTFE calibration mask 1 aaaaa 01001 data  
Load GTFE trigger mask 1 aaaaa 01010 data  
Load dac's 1 aaaaa 01011 data  
Load mode register 1 aaaaa 01100 data  
Load dac's 1 aaaaa 01011 data  
Read data mask 1 aaaaa 10000  
Read calibration mask 1 aaaaa 10001  
Read trigger mask 1 aaaaa 10010  
Read dac register 1 aaaaa 10011  
Read mode register 1 aaaaa 10010  
GTFE commands. aaaaa are the five bit GTFE address. The first bit (most left one) is the MSB.

Registers

The GTFE64 has five registers.
  1. Data mask
  2. Calibration mask
  3. Trigger mask
  4. Threshold and calibration dac's
  5. Mode and deaf register.
Register values are sent in 68 bit data format. The tables below how the register values are packed into the 68 bits.

Mask Registers (data,calib,trig)

The next table shows the data format for the three mask registers. B0-B67 are the 68 data bits, the MSB (bit 67) is sent first. The second row (S0-S67) counts the bits in the order they are sent to the GTFE.
B67 B66 - B48 B50 B49 - B34 B33 B32 - B17 B16 B15 - B0
S0 S1-S16 S17 S18 - S33 S34 S35 - S50 S51 S52 - S67
1 ch63 - ch48 1 ch47 - ch32 1 ch31 - ch16 1 ch15 - ch0


Threshold abd Calibration DAC

Threshold and Calibration DAC's. Each DAC has seven bits. One bit selects high/low gain the other six bits are the value. The following table shows how the bits are placed in the data. C0-C5 are the six calibration DAC bits (C0: LSB) and CR is the range selector bit. T0-T5 and TR are the corresponding bits for the threshold DAC.

B67-B12 B13B12B11B10B9B8B7 B6B5B4B3B2B1B0
S0 - S53 S54S55S56S57S58S59S60 S61S62S63S64S65S66S67
  C0C1C2C3C4C5CR T0T1T2T3T4T5TR

Mode Register

The mode register contains only two bits. One bit sets the read directions of the GTFE (0: left, 1: right) and the second bit sets the "deaf" bit. If this bit is set to one, the GTFE disables the trigger signal from the previous chip.

GTFE64D version 1: In order to write the mode register for GTFE64D version 1 the directions and deaf bit are shifted by one bit to the left within the data.

B67-B3 B2B1B0
S0 - S64 S65S66S67
  0dirdeaf
for GTFE64D ver1 dir(v1)deaf(v1)0
Last modified: Fri Jun 1 15:45:26 PDT 2001