import vme
import wkUtil
import array

access = 0x3
dwidth = 0x4



class ComDaq :

    """ GLAST Comunication VME module.

    Com is a I/O acquistion board.
    """


    def __init__ (self) :

        self.baseAdr = 0



    def setBaseAdrs (self, baseAdrs) :
        """ Set the VME base address for the COM-board. """

        self.baseAdrs = baseAdrs

        self.adrsCtrl = self.baseAdrs
        self.adrsStat = self.baseAdrs + 0x4
        self.adrsOut = self.baseAdrs + 0x8
        self.adrsIn = self.baseAdrs + 0xc

        print "%x %x %x %x" % (self.adrsCtrl, self.adrsStat,
                              self.adrsOut, self.adrsIn)

    # ==================================================

    def cntrlReg (self) :
        """ Return controll register content. """
    
        return vme.VMEin (access, self.adrsCtrl, dwidth)


    def statReg (self) :
        """ Return status register content. """

        return vme.VMEin (access, self.adrsStat, dwidth)


    def printReg (self) :
        """ Print the controll and status register content. """

        ctrl = self.cntrlReg()
        stat = self.statReg()
        print "Control = %x, Status = %x " % (ctrl,stat) 


    # ==========================================================

    def reset (self) :
        """ Reset the control Register. """

        vme.VMEout(access, self.adrsCtrl, dwidth, 0x0)
        vme.VMEout(access, self.adrsCtrl, dwidth, 0xf000)
        
    

    # ==========================================================

    def setBit(self, bit, value=1) :
        """  Set a bit in the controll register to zero or one.
        
        ex.: setBit(29) or setBit(29,1) sets bit 29 to one.
        setBit(29,0) sets bit 29 to 0.
        """
        
        ctrl = vme.VMEin (access, self.adrsCtrl, dwidth)
        
        bitToSet = 0x1 << bit;
        if value == 0 :
            ctrl &= ~bitToSet
        else:
            ctrl |= bitToSet

        print " set bit %x   %x" % (bitToSet,ctrl)
        vme.VMEout(access, self.adrsCtrl, dwidth, ctrl)


    # ==========================================================
    #
    # ==========================================================

    
    def setPlay(self) :
        """ Configure the module so that the FIFO's are ready to
        be played.
        """

        ctrl = vme.VMEin (access, self.adrsCtrl, dwidth)
        ctrl = ctrl & 0x7fff5fff

        print " %x" % ctrl
        vme.VMEout(access, self.adrsCtrl, dwidth, ctrl)

        ctrl |= 0xf000
        print " %x" % ctrl
        vme.VMEout (access, self.adrsCtrl, dwidth, ctrl)
        
        vme.VMEout (access, self.adrsStat, dwidth, 0xff00)

        

    # ==========================================================
    #
    # ==========================================================


    def play(self) :
        """ Plays the Fifo's once.
        """

        ctrl = vme.VMEin (access, self.adrsCtrl, dwidth)
        ctrl |= 0x8000f000;
        vme.VMEout(access, self.adrsCtrl, dwidth, ctrl)

    # ==========================================================
    #
    # ==========================================================
 
    def replay(self) :
        """ start acquistion using the previous content of the out FIFO.
        
        control register: set bit 15 and 31 are set to 0 (stop acquisition,
        reset in-FIFO (reset data, no conf). \n
        set bits 12-15 to 1 (not reset FIFOs. \n
        start acquistion (bit 31 = 1).
        """

        ctrl = vme.VMEin (access, self.adrsCtrl, dwidth)
        ctrlNew = ctrl & 0x7fff7fff;
        vme.VMEout(access, self.adrsCtrl, dwidth, ctrlNew)
        ctrlNew = ctrl | 0x0000f000;
        vme.VMEout(access, self.adrsCtrl, dwidth, ctrlNew)
        ctrlNew = ctrl | 0x8000f000;
        vme.VMEout(access, self.adrsCtrl, dwidth, ctrlNew)
        
        # print "replay %x " % ctrl

    # ------------------------------------------
    #    FIFO Delays
    # ------------------------------------------


    def setChan0Delay(self, delay) :
        """ Set the Delay of channel 0. The step size is about 1ns.
        """
 
        ctrl = vme.VMEin (access, self.adrsCtrl, dwidth)
        print "Fifo Delay %x" % ctrl
 
        ctrl &= ~0x3f
 
        ctrl |= delay & 0x3f
        vme.VMEout (access, self.adrsCtrl, dwidth, ctrl)
        print "Fifo Delay %x" % ctrl

    #
    # 
    #
    
    def fifoDelay (self) :

        ctrl = vme.VMEin (access, self.adrsCtrl, dwidth)

        inFifoDelay = (ctrl >> 16) & 0xff 
        dataClkDelay = (ctrl >> 6) & 0x3f 
        chan0Delay = ctrl & 0x3f 
    
        return dataClkDelay, inFifoDelay, chan0Delay 


    def fifoRdBackDel (self, delay) :
        ctrl = vme.VMEin (access, self.adrsCtrl, dwidth)
        ctrl &= 0xfffff03f
        ctrl |= (delay << 6) & 0x00000fc0
        vme.VMEout (access, self.adrsCtrl, dwidth, ctrl)

    # ------------------------------------------
    #    Dump the input-Fifo
    # ------------------------------------------


    def dumpFifo (self, loops=10) :
        
        for i in xrange(loops) :
            data = vme.VMEin(access, self.adrsIn, dwidth)
            
            print "%4d  %s" % (i, wkUtil.intToBitStr (data))



    # ===================================================
    #     read data fifo
    # ===================================================

    def getFifo(self, nWords, nSkip=0) :
        
        data = array.array('l')
        data.extend( nWords * array.array('l', [0]) )


        # read from 0 to nSkip but don't save data

        adrsIn = self.adrsIn
        
        for i in xrange(nSkip) :
            vme.VMEin(access, adrsIn, dwidth)

        # save data in data array
        
        for i in xrange(nWords) :
            data[i] = vme.VMEin(access, adrsIn, dwidth)

        return nWords, data




    # --------------------------------------------
    #  Load output FIFO
    # -------------------------------------------


    def loadFifo (self, bitList) :

        for row in bitList :
            vme.VMEout(access, self.adrsOut, dwidth, row)
                       
            
    # clock

    def clockOn(self) :
        self.setBit(29,1)
        
    def clockOff(self) :
        self.setBit(29,0)

    def resetFifo (self) :
        """ Reset the control Register. """

        ctrl = vme.VMEin (access, self.adrsCtrl, dwidth)
        ctrl |= 0xf000;
        vme.VMEout(access, self.adrsCtrl, dwidth, ctrl)