TMCM for EM mini-tower

Test Procedure

Power Consumption (TM702)
- DVDD(2.5-3.0V), AVDDA(1.5V), AVDDB(2.5-3.0V) were turned on and their current draws were measured.
- The measurements were done with/without a 20 MHz clock signal on both the left and the right directions and with module addresses of 0 and 5.
GTRC LVDS output level (TM708)
- Voltages of the LVDS output signal of both left and right GTRCs were measured in module addresses of 0 and 5.
GTRC configuration register load and readback (TM704)
GTFE configuration registers (TM705)
Broadcast GTFE configuration register load (TM705)
GTRC addressing (TM707)
Read-event sequence
- All channel mask and trigger mask were enabled, and one of every 13 channels, such as [0,13,26,39,52], of calibration mask, was enabled for all GTFEs. A calibration strobe was initiated, followed by a trigger, and layer-OR and data were read out. The output data were checked to agree with the pattern of the calibration mask.
- The data of GTFEs addressed with 0 to 11 were read out to the left-hand side and the data of GTFEs from 12 to 23 were read out to the right-hand side.
- The test was repeated by another calibration-mask pattern, one-bit shifted, until all 64 channels were covered.
Layer-OR threshold scan
- All trigger mask of one of 24 GTFEs are enabled and layer-OR rates were measured changing the threshold DAC count from 0 to 14 in low range.
- The test was repeated one by one for all 24 GTFEs and for both the left and the right layer-OR signals.
SSD bias leakage current (TM703)

Brief Test Summary

SN	RC	FE	PA	Dest	EN	Test date	Loc	DVDD_V [V]	AVDDA_V [V]	AVDDB_V [V]	DVDD_I [mA]	AVDDA_I [mA]	AVDDB_I [mA]	BIAS_I [nA]	RCreg	FEreg	EVdat	TRG_L	TRG_R
70	3	F2	Y	Italy	N	12/19/2002	TELE	2.936	1.451	2.938	69.873	66.650	12.891	16.740	--	--	NG	--	NA
70	3	F2	Y	Italy	Y	01/17/2003	UCSC	2.899	1.453	2.932	65.576	65.185	12.891	15.802	--	--	NG	--	--
71	3	F2	Y	Italy	N	12/19/2002	TELE	2.939	1.452	2.939	69.824	66.064	12.695	21.017	--	--	--	--	NA
71	3	F2	Y	Italy	Y
72	3	F2	Y	Italy	N	01/31/2003	TELE	2.899	1.453	2.931	67.236	66.064	12.695	14.306	--	--	--	--	--
72	3	F2	Y	Italy	Y
73	3	F2	Y	SLAC	N	01/31/2003	TELE	2.897	1.452	2.931	67.676	65.283	12.353	28.635	--	--	--	--	--
73	3	F2	Y	SLAC	Y
74	3	G	Y	Italy	N	01/16/2003	TELE	2.668	1.443	3.296	59.717	76.855	23.389	17.706	--	--	NG	--	--
74	3	G	Y	Italy	Y	01/24/2003	UCSC	2.897	1.455	2.925	69.092	63.281	19.189	18.310	--	--	NG	--	--
75	3	G	Y	Italy	N	12/20/2003	TELE	2.934	1.455	2.927	74.707	64.111	26.123	18.032	--	--	NG	--	NA
75	3	G	Y	Italy	Y	01/17/2003	UCSC	2.897	1.453	2.924	68.164	62.988	18.945	18.798	--	--	NG	--	--
76	5	G	Y	SLAC	N	01/16/2003	TELE	2.698	1.448	3.293	70.752	75.586	29.980	18.813	--	--	NG	--	NA
76	5	G	Y	SLAC	Y	01/23/2003	UCSC	2.898	1.456	2.919	64.746	61.865	25.098	22.133	NG	NG	NG	NG	--
77	3	G	Y	Italy	N	12/19/2002	TELE	2.937	1.455	2.934	69.629	64.551	20.557	15.686	--	--	NG	--	NA
77	3	G	Y	Italy	Y	01/17/2003	UCSC	2.898	1.455	2.924	65.722	63.037	20.117	15.811	--	--	NG	--	--
78	3	G	Y	SLAC	N	12/19/2002	TELE	2.937	1.430	2.920	76.221	109.033	42.480	16.204	--	NG	NG	NG	NA
78	3	G	Y	SLAC	Y
79	3	F2	Y	Italy	N	12/19/2002	TELE	2.937	1.454	2.937	69.629	62.353	13.037	19.949	--	NG	NG	--	NA
79	3	F2	Y	Italy	Y	01/17/2003	UCSC	2.899	1.454	2.929	65.234	65.234	12.744	16.487	--	NG	NG	--	NG
80	3	F2	Y	Italy	N	12/19/2002	TELE	2.934	1.453	2.935	78.076	66.064	13.086	17.301	--	NG	NG	NG	NG
80	3	F2	Y	Italy	Y	01/22/2003	UCSC	2.896	1.454	2.931	71.826	64.209	12.891	16.530	--	NG	NG	NG	NG
81	5	F2	Y	SLAC	N	12/19/2002	TELE	2.939	1.454	2.935	66.650	66.113	12.793	17.712	--	--	--	--	NA
81	5	F2	Y	SLAC	Y	01/22/2003	UCSC	2.901	1.453	2.926	62.500	64.160	12.598	18.853	--	--	--	--	--
82	3	G	Y	Italy	N	12/19/2002	TELE	2.938	1.444	2.931	69.092	78.418	21.387	17.074	--	NG	NG	--	NA
82	3	G	Y	Italy	Y	01/22/2003	UCSC	2.898	1.444	2.925	65.234	75.000	20.752	NA	--	NG	NG	--	NA
83	5	F2	N	SLAC	N	01/19/2003	UCSC	2.897	1.452	2.930	67.773	66.406	12.549	18.731	--	--	--	--	--
83	5	F2	N	SLAC	Y
84	5	F2	N	SLAC	N	01/19/2003	UCSC	2.897	1.452	2.930	67.334	65.527	12.646	14.965	--	--	--	--	--
84	5	F2	N	SLAC	Y

SN : serial number
RC : version of GTRC chips (3 or 5)
FE : version of GTFE chips (F2 or G)
PA : pitch adaptor is attached or not (Y or N)
Dest : destination place
EN : encapsulated or not (Y or N)
Test date : test date
Loc : test location
DVDD_V,AVDDA_V,AVDDB_V : voltages of power lines [V]
DVDD_I,AVDDA_I,AVDDB_I : currents of power lines [mA] under a 20-MHz clock signal and a module address of 0.
BIAS_I : leakage current [nA] of detector bias line at 200 V.
RCreg : functionality of GTRC control registers: TM704 and TM707 (---(good) or NG)
FEreg : functionality of GTFE control registers: TM705 and TM706 (---(good) or NG)
EVdat : functionality of reading event data (---(good) or NG)
TRG_L, TRG_R : trigger propagation (---(good), NG or NA(no data) )

Known problems

SN	GTFE Adrs. or GTRC	Status
70	23	This chip does not work for read-event-data when event buffer #1 is used.
71
72
73
74	0	This chip does not work for read-event-data at all.
	1	This chip shows oscillation up to a threshold of at leat 14 DAC counts.
	2	This chip shows oscillation up to a threshold of at leat 14 DAC counts.
	10	This chip does not work for read-event-data when event buffer #1 is used.
	13	This chip does not work at all for read-event-data. It always shows TAG error and the data is collapsed.
	18	This chip does not show any event data when event buffer #0 is used.
75	1	This chip does not work for read-event-data when event buffer #0 is used.
75	23	Afer encapsulation, this chip is showing oscillations up to a threshold of at leat 14 DAC counts.
76	22	This chip shows oscillation up to a threshold of at leat 14 DAC counts.
	23	This chip does not transfer event data in the left-hand direction.
	GTRC left	Afer encapsulation, any operation from the right-hand side does not work.
77	11	This chip shows oscillation up to a threshold of at leat 14 DAC counts.
78	All	This TMCM does not work at all other than reading-out of GTRC control registers.
79	8	This chip does not respond well for reading out control registers from the right side. It works well from the left side
	16	This chip shows a very peculiar behavior when the calibration channel patter [0,13,26,39,52] is used. In that case, it returns the data [0,13,26,38,52]. All other calibration patterns work well.
	8 or 9	In the right-hand direction, the layer-OR signal is not seen from chip address 0 through 8.
80	3	This chip does not respond at all but does pass data and trigger (with one exception noted below).
	2 or 3	In the right-hand direction, the layer-OR signal is not seen from the chip address 0 through 2
	20 or 21	In the left-hand direction, the layer-OR signal is not seen from the chip address 21 through 23
81
82	7	This chip does not respond well when reading the control registers from the right side. It works well from the left side.
	10	This chip frequently shows bad event data (channels other than those that were pulsed). It may be due to oscillations but has not been understood in detail.
	12	Channels from 40 to 50 in this chip do not show hit-event data when calibration pulse is sent. This problem appear after encapsulation.
	15	This chip does not work for read-event-data when event buffer #0 is used.
83
84

Photo

in the car coming back from the test at Teledyne.

sugizaki@scipp.ucsc.edu

Last modified: Thu Feb 6 23:56:09 PST 2003