Wafer test in fall 2002
Wafer layout
Test results
- Note:
*1: Current draw of DVDD(2.5V), AVDDA(1.5V), AVDDB(2.5V)
just after power-on without clock signal.
*2: Trigger-out count rates of only a channel #8 enabled
for threshold DACs changed from 1L to 50H, measured without clock signal
when 0.5 sec passed since threshold DAC register was set at each value.
*3: Trigger-out count rates of all 64 channels enabled, measured in the
same condition with *2.
*4: Results of functionaliy tests performed. The numbers on the first line
in text data, 2xx, corresponds to test ID# in TD-247.
Test setups
sugizaki@scipp.ucsc.edu
Last modified: Mon Jan 13 22:37:13 PST 2003