External Trigger

There are two ways to accept an external trigger request to the TEM. The L1T FPGA has external trigger request inputs named, EXT-TREQ, CAL-TREQ and ADCH-TREQ. The other possibility is to feed the trigger request directly into the L1T input of the TEM.

Using FPGA Treq inputs

The external TREQ could be connected directly to the one of the FPGA's TREQ inputs. Because the TREQ's are not connected to any connector, it has to be connected to the FPGA's pins. The following table shows on which pin the TREQ's are located. The signal is a CMOS signal.

Name	Pin
EXT_TREQ	P8, 15
CAL_TREQ	P6, 16
ADCH_TREQ	P8, 9

In order to protect the FPGA, we are using a TTL buffer that obtains it's power from the VME backplane.

Using L1T input

Instead of using the external TREQ one could use the L1T input. The following figure shows how to connect the external TREQ to the L1T input. It also connects the internal generated TREQ (L1T_out) so that one could still use TREQ's generated withhin the TEM (software trigger, calib strobe, self trigger).

The External TREQ has to be at least two clock cycles wide. Also if a scheme is used as shown the external TREQ shows up also at the L1T_out output and feeds back into the Or-gate. Therefore the external TREQ has to be long enough so that it is still active when it feeds back to the Or-gate (see figure below). Typically a 1-2 mus wide signal is used. The TEM uses active low state logic for the lvds signals. If the output is in the high state (output+ > output-) it is a logic zero. (??)

Last modified: Tue Oct 3 08:11:39 PDT 2000