import sys
import array
from time import sleep
import GtfeReg


sys.path.append('/home/babar/wilko//glast/presto/proj0/src')


import tkrTem

#
# initilize the VXI library
#


tem = tkrTem

stat = tem.tkrVMEInit (0x8000000)
print 'open VXI lib: ', stat


#
#  load FPGA register
#

stat = tem.tkrLoadDataFifo('../../conf/tkrrdout2_0.ttf')
print stat
stat = tem.tkrLoadL1tFifo('../../conf/l1t2_0.ttf')
print stat 
tem.tkrLoadFinalize()


tem.temReset()
tem.temR()

tem.temEnableCable(5) 




fee = GtfeReg.GtfeReg(tem)