Minutes of the Tracker Electronics Meeting June 5, 2000 Present: David, Robert, Hartmut, Masa, Ned, Dieter, Gunther, Vallon, and Wilko 1. Planning for the heavy ion beam test in Japan (Masa). Robert: The current thinking is to test the 0.5um front-end chip and test for latch-up. Our Japanese colleagues also want to irradiate detectors and look for leakage current increases. Hartmut: He would like to test the silicon detectors as well for possible damage from heavy ions (e.g. capacitor breakdown?). Robert: The current heavy ion beam does not produce enough heavy ions to test fully to the required minimum threshold of 8 Mev/mg/cm^2 (from the GLAST IRD). The current system only allows for 1.5 Mev/mg/cm^2 at full beam energy. We might get 10 Mev/mg/cm^2 by slowing down the ions in an absorber. He also noted that the HP 0.5um process has been shown to have an SEL threshold of 60 Mev/mg/cm^2 with the standard design rules. Hartmut: We may want to install a resistor in the power line to the test chips so that the chip is protected after a latch-up has occurred. The resistor value would be on the order of 500 ohms to 10K ohms. He stated that the latch-up condition might clear after the power to the chip sags below something like a volt, but probably it is necessary to cycle the power. The test would simply count total latch-ups by monitoring the power line to the test chip. Robert: We may be able to use an IR laser to test for latch-ups as well. There is some concern on how to calibrate the system. Hartmut: He raised his concerns about possible problems due to the split grounds in the current front end chips while testing for latch-ups (the HP 0.5um test chip to be tested does not have this feature). He also noted that this is not the final chip and we will both gain some experience and maybe set the lower limit where the HP 0.5um is sensitive. 2. Progress on BTEM trigger testing (Wilko). Wilko: He is continuing tests on the BTEM for readout noise that causes the front-end chips to retrigger. The current tests take about ˝ day to complete. He believes he understands this and has a fix that will allow for expedient testing. Wilko has started the testing of the Italian switching power supply. He has turned it on and observed the output holds at 4.98 volts with the input voltage adjusted from 17 volts to 120 volts. He will connect this supply to the tracker test system and study noise injection issues from this new power source. Robert stated that Roger Williamson and company would provide a power supply test system that will generate a controlled noise source so tests on tracker susceptibility to power supply noise could be studied. Dave: He will find out what the specifications were for the BaBar vertex detector. This document could be used for a basis for us to specify the tracker power requirements. Ned: He noted that the BaBar vertex detector did not meet the noise limit of the front-end amplifiers by a factor of two or so. He warned that the added noise could be from the power supply system. Robert: Noted the ACD system folks at Goddard are also interested in testing the tracker in the presence of their PMT power supplies. UCSC has a sample from them, which Wilko should try out. Ned noted that any interference there would depend critically on the metal grounding arrangement between the two systems. 3. Progress on the command decoder test chip (Ned). Ned: The test chip was sent off to Mosis this morning. Spice, DRC and LVS checks all passed. Mosis’s initial checks all passed as well. Ned noted that the new Tanner upgrade now takes 5 hours to run this schematic in TSPICE for 2 microseconds when the previous version ran in 20 minutes. The decoder chip used “low-power” SCMOS SUBM standard cells with lamba=0.3um, which Ned modified to separate the ground metal from the substrate contacts, while still maintaining the original substrate contact locations. He used the Tanner auto place and route. 4. Plans for a paper on the BTEM readout system. Status of the single-ladder test board for making the required measurements (Masa and Wilko). Robert: A NIM paper needs to be produced for submission by the end of summer. This publication should not cover previous NIM papers on the amplifier and discriminator but just reference them. Masa produced an outline for this paper. Measurement results will be used from the tracker test system, which comprises one front-end chip, one controller, 32 channel tracker strips (“baby detectors”) with three in series to form a 32cm long tracker. Wilko will help with tests and performance measurements. Students may also help. It was noted that Wilko could use another dedicated TEM board, so that this test system and the BTEM could be run in parallel. David: He will see Roger and James about making three total: One for Roger, one for Wilko and one for our Italian colleges. 5. Analysis of the amplifier/discriminator chip (Dieter). This is put off one week. 6. Issues with conversion of the layout from Cadence to Tanner (Vallon). Vallon: Several problems occurred with translations, and he suspects that we will not be able to simply scale the Cadence cells to the new process and new design tools. This will be investigated further by Vallon and Ned. Robert: Gerrit Medeller took the original Mentor Graphics design by Pavel Poplevin and converted to Cadence in order to finish the chip (except for the command decoder, which was done in Cadence by auto place-and-route). 7. CAD tools for controller chip redesign. Robert: He stated we need to find the best approach for the final design and fabrication. Gunther: Tanner will quit if designs are too large. The controller chip should be small enough. Tanner has an advantage of being nicely packaged for Mosis, with standard cells and technology files all in place. Gunther gave his view that the controller chip should be done completely in VHDL. Several options such as Exemplar Leonardo exist for logic synthesis, but the conclusion was that Tanner will do everything we need as far as standard-cell place-and- route is concerned and DRC/LVS. 8. AOB None. Action Items: 1. Masa and Tsune: set up a test chip with a resistor in series with the power and test for latchup with a laser. 2. Wilko: try running the PMT supply connected to the tower and do noise scans. 3. Dave: find specs for the BaBar SVT power supplies. 4. Dave: talk to Roger about making more TEM boards. 5. Vallon and Ned: investigate whether the existing lambda=0.4um layout can be rescaled to 0.3um and imported into Tanner LEdit.