Minutes of the Tracker Electronics Meeting 
June 19, 2000

Present: David, Robert, Hartmut, Masa, Dieter, Gunther, Vallon, Wilko, and
Tsune

Agenda: 
1.      Dave & Dieter: status of the analog front-end schematic 

The changes are nearly complete. This design has reduced the power in the 3.3-volt supply by a 
factor of 4.  Robert will review the changes when he comes to SLAC Wednesday June 21 at 
10AM. Robert raised some concern if the preamp and shaper can be probed because of 
capacitance loading. Dieter didn’t think there is much of a problem with driving probes. He agreed 
to add a buffer if needed.

2.      Ned and Vallon: status of the layout translation from Cadence to Tanner 

Ned is making good progress with Tanner tools. There still are some issues of grid alignment that 
need to be cleared up when the Tanner technical support person gets back from vacation. Ned is 
also trying to port Cadence basic cells (originally laid out by Pavel and Vallon) to Tanner. He is 
optimistic overall that Tanner will work. Ned will try to open some 0.8um cells in Tanner and see 
what happens. Ned does have more work understanding these tools before he is comfortable 
with knowing he can go from the start to end of a project.

3.      Robert: modification and simulation of the Viewlogic schematic. 

Robert: We need to replace the data shift in and out to LVDS signals from CMOS differential. We 
need to make sure the timing is still ok. Robert asked who might be able to update the Viewlogic 
schematics. Vallon offered to enter the schematic changes, after a long silence. One other 
change to implement is the writing out of the buffer pointers.

4.      Masa & Tsune: status of the SEL testing 

There was more discussion of what the test setup looks like. The amplifier needs some 
capacitance on the power pin to prevent oscillations. The type and size of capacitors were 
discussed. Ned recommended using NPO type capacitors because of the good high frequency 
characteristics. The chip may be damaged when latch-up occurs if too much capacitance is used. 
Masa believes the testing the chip using the laser will occur this week.

5.      Dieter et al: SEU hard cell for the front-end chip

No progress. Dieter is full time on preamplifier.

6.      Robert: Getting the Verilog code for the controller chip 

Robert:  He is working on this. He will need Garret’s help.