Tracker new GTFE design meeting

Action Items: Chip design

1. Put in stray capacitance in the shaper.
2. Clean up the resistance equation on bottom right side of shaper schematic
3. Ned asked for the voltage drop across MN5 in the shaper is increased from 0.3V to 0.4V.
4. Need to look closer at the matching of discriminator pair in the comparator circuit. The goal is to make 
the variation in offsets be small as compared to one sigma noise which is 20mV RMS. We agreed that 
we want better than 5mV RMS variation and the goal is 2mV RMS. It was noted that the lengths of 
MP1 and MP2 could be increased.
5. Ned is concerned with wiring going from the reset circuit to the front-end input. We decided that the 
two reset functions would be globally disabled separately.
6. The test chips will have approximately eight channels. 
7. The front-end transistor, MP13, width will be sized to 1500um from the current 3300um.
8. One channel in the test chip will have a 300um MP13. This is to see where the limit of sizing MP13 is.
9. A probe pad will be put on the shaper output but no buffer.
10. Robert will find the HSPice rules for flicker noise.

Action Items: Layout.

1. We will use the HP 0.5um as our base line.
2. David will find what Peregrine costs and yields.
3. Prototype design will adjust DRC to 0.3u lambda base.
4. We need Cadence set from um to 0.3 lambda.
5. We need HP 0.5um revised to um.
6. Latch-up and SEUs.
A. We will use minimum size HP
B. We will go forward on the SEU/latch-up prototype chip using Ned’s design. We will use this chip 
in a test beam. We will also implement registers in the standard design for comparison.
C. We will implement the Ned latch-up design in the GTFE layout.