Minutes of the Tracker Electronics Meeting

November 27, 2000

Ned said that he has placed the schematics and layouts of the Tanner cells on the unix "incoming" directory. He modified the names of the SEU-safe cells to conform to the same convention as the other cells.

Robert said that he was still having trouble getting the digital simulation working (problem has been fixed since then).

Dieter would like documentation of the chip. Robert said that Dave is supposed to be working on updating the GTFE64 interface description document.

Dieter talked about simulation of the GTFE64 front end. He said that the gain is 250 mV/fC (based on feedback and coupling capacitor values alone) without any differentiation in the shaper. With integration time=differentiation time that should drop to 1/e, or about 94 mV/fC. This agrees with the simulation at very low amplitudes. However, the system is very non-linear, so at 1-MIP amplitudes the gain appears to be quite different. The same goes for the shaping time. He suggests looking at 1/10 MIP to see the true (linear-amp) shaping time. It now peaks at about 1.5 us at such low amplitude. Ned said he would like to see the shaper output for the range Q=0.7 to 2 fC in about 0.2 fC steps. Dieter said the simulated noise is 20 mV at the shaper output.

Dieter said that he is putting into the MOSIS test chip some clock receivers with matched transistors: 3 um wide times 2 (mirrored symmetric pair) for each of the two differential input transistors. The width in the old design was 24 microns times 1, so the total width is down by a factor of 4, but Dieter expects that the improved layout will more than make up for that in terms of matching. However, there are no data in either case to use for making a quantitative prediction.

Dieter said that he was able to simulate the entire 128-stage shift register in spice for the test chip.

Ned said that he talked to Tanner and found that TPR (Tanner Place & Route) should be able to run off of an EDIF netlist, meaning that we should be able to work from the Viewlogic schematics via EDIF. He will experiment with this.

There was some discussion of the pad frame. It no longer needs the standard corners, since we have to break anyway between analog and digital sides of the chip. Dieter said that it may not make sense to use the standard pads with their huge protection structures on the outputs, since those connect to drains, not gates, and therefore should be much less sensitive to ESD.

Wilko said that he is still working on analysis of the noise data.