Minutes of the Tracker Electronics Meeting

January 29, 2001

Present: Robert, David, Masa, Wilko, and Dieter

1. GTFE simulation: Robert; Robert reported that he Pspice simulated inverters for delay measurements. He made the following measurements at 3.3 VDD.

One inverter 90pS, Four inverters 200pS, Eight inverters 330pS. He then made the measurements again at 2.5 volt VDD. He reported that delay measured 250pS for one inverter. The conclusion is that the gates are slower at 2.5V, as expected, but not enough to be worried as long as the fanout does not exceed 4 to 8.

2. GTFE layout: Ned; Ned reported that layout is going well and he may start simulation soon. He also reported that he would start Max on Spice simulation of digital components.

3. Test chip: Masa; Masa stated that he started testing the HP 0.5um test chip that we received from MOSIS. He reported that he used 1, 2, 4, 5 fC inputs and 1, 2, 4, 5 MIP input signals. He reported that he observed 3.5uS peaking time. Dieter reported that this is consistent with the simulation runs for the submission. There was some confusion about the operation of the chip. Robert asked that Dieter and David send more documentation and schematic and/or PSpice files so Masa can understand the operation of this chip. Robert also asked for some test procedures from Dieter so Masa can test all the features.

4. LVDS testing: Wilko; Wilko reported that he tested the sensitivity of the clock receivers on one MCM. He stated that the duty cycle of the probed output of the clock receiver started increasing when going below about 35mV on each leg. He reports a few chips started to fail below 35mV and many of the chips worked down to the 15mV level. All chips worked at 50mV with no observed problems. Robert also noted that Ned was comfortable with this signal above 100mV. Robert decided that we should not drive the GCFE below the 100mV single ended voltage. David stated that this should work since we have reduced the signal from the current 750mV level and converted to current drive.

5. MCM: David; David stated that the layout work is in progress. Gwelen planned to come to SLAC to look at the layout but didn't make it. Robert suggested we e-mail the PADS file to UCSC. David stated he would send it.

6. KAPTON cable: David; David stated that the Kapton cable layout is still in BJ's and Gwelen's camp. David will assemble a layout as soon as the DXF file as soon as one is ready. Robert stated that there is concern about the length of the cable and having more than one vender bid on it. He stated that we should look at the possibility of splicing two cables to make one and at least keep that as a backup as long as there is only a single vendor for the full-length cable.