Minutes of the Tracker Electronics Meeting
March 19, 2001
1. Robert reported on his simulation of the chip-to-chip driver/receiver set. He will try to improve the performance of the comparator of the clock receiver, to be more sure the pick off the crossing time of the input differential clock signal. The existing comparator output even from the second stage rises no more quickly than the 6 ns risetime input clock. The simulations show that a mismatch in clock timing greater than about 3 ns from one chip to the next will screw up the data transfer. If the input clock risetime is long, then there is some potential for problems if the comparator is not sufficiently accurate.
2. Wilko said that he will be going to the balloon flight TEM meeting Wednesday at SLAC.
3. Robert reported that his Spice simulations of the GTFE64 digital logic works the same at 40 MHz as it does at 20 MHz.
4. Dieter has been working on front-end simulations and will send the results to Wilko. Then UCSC will modify the DAC design appropriately.
5. Dieter sent new schematics and layout revisions of GTFE64 front-end to UCSC.
6. Masa checked out his amplifier noise measurement setup and is ready to measure noise and gain of the HP test chip. He will repeat the measurements with the Peregrine chip once the system is going well.
7. Ned reported that the front-end chip control circuitry (ctrl2) mostly updated with Robert’s changes. He also completed the fanout between analog cells and the mask registers. This fit well on top of the wall that divides the digital and analog sections. He has a spot picked out on the analog side to put in the buffers for the calibration mask clock and control signals. Power distribution from the rear pads to the front analog cells is in place. He checked that the 17um shift of input pads is okay with Gwelen (and will be documented). Remaining layout work: power on circuitry, external calibration input, DACs, connections to pads.
8. Wilko reported on progress in planning the test systems. He now intends to use TEMs to test MCMs at the factory and during burnin. We will use a logic analyzer for wafer testing. He plans to put a working MCM behind the one under test to check all IO to controller chip. However, we need a new logic analyzer. An HP one is available for $12K to $14K which has an internal disk and ethernet port.
9. Masa & Mutsumi will start on planning an interface board from the logic analyzer to the wafer probe. The will also give it capability to talk to an MCM board.
10.Ned said that Atlas is making progress with reducing the stepper motor pickup on the UCSC wafer probe station.
11.Robert suggested that we build into the probe cards pads for capacitors and so forth.
12.Masa will help Mutsumi get started on SEU/SEL testing of Dieter’s new chip.