Wed, 19th July, 2000
Tracker Meeting

Perugia, Trieste, UCSC, SLAC, Hytec

Ossie reported on his visit to the Semicon West conference: he mainly talked to vendors 
of adhesives and clean room supplies.  From AI tech he found that they have one material 
that is a NASA approved compliant adhesive (the one that we have already seen the spec 
sheet on).  The engineer was not encouraging.  In particular he had doubts about gluing 
lead.  The potential problem is aging of the surface.  Tungsten is more resistant to 
oxidation.  Steve at Hytec mentioned that they used a primer on the lead before gluing.  
Gwelen said that he once had a Lead Engineers Handbook from the library, which might 
be useful to get again.

John said that tungsten is also much better than lead for the thin converter layers in terms 
of handling during assembly.

Gwelen reported on his visit to Semicon West.  He looked at  
1. plasma cleaners (for the hybrids).  Plasma cleaning can increase the reliability of wire 
bonding, as has been well documented by others.  He would like to clean the hybrid 
after mounting of parts and chips.  A machine is too expensive ($40k to $50k), but the 
work can be contracted out. 
2. Bond pull testers.  The good ones are automatic, which makes them much more 
consistent that what we have.  It is also possible to do non-destructive testing.  The 
cheapest run about $10k.  
3. Adhesives and Encapsulants.  He got a couple of ideas to relay to Bill with regard to 
the hybrid encapsulation.

Roberto suggested to do pull tests before and after plasma cleaning to judge whether it 
really is important.  Ossie remarked that there may be large time lapses during assembly 
that could result in deterioration of bonding pads.

Ossie reported on an adhesives testing meeting that he had with Martin & Roman.  
Roman wrote up notes on the meeting (see attachment).  He said that one thing that they 
think is important to do is to characterize Silicon under stress.  

Ossie has talked to a dicing vendor.  They believe that they can hold a 10um tolerance on 
the wafer width.  Total cost will be close to that of laser-cut wafers but requires 
interacting with several vendors.  The cost is $7.50 for dicing one wafer.  Including Al 
coating, grinding to thickness, and dicing comes to about $29/sample.  There is no quote 
yet on laser marking, but it is probably about $10/wafer for simple marking.  Gwelen said 
that he can find a good piece of Si for testing laser marking.

Gwelen gave us the status on the new thermal test fixture.  The layup is finished for C, 
Pb, Kapton plus wiring.  He found that the Ag glue is out of date, slightly, so he ordered 
new samples of glue.  UCSC will start soon temperature ramping tests on the completed 
baseplate.

John reported that he is continuing work on design of the adhesive dipping fixture.

Robert showed 3 plots of results from Jose’s simulations of carbon-fiber walls versus 
aluminum walls (see attachment).  The former are 4.4% R.L. and the latter 8.8% R.L. 
(going from one tower, through 2 walls, and into the next tower.  The size of the tails is 
defined to be the ratio of the 95% width of the PSF to the 68% width, which for a 
gaussian should be 2.  The requirement on this ratio is that it should be less than 3.  One 
plot compares just the 68% width for thick walls versus thin walls, and no significant 
difference is seen there.  The other plots compare the tails for the two configurations.  
Again, nothing significant is seen for the back (thick-converter) section, which is 
expected, given the huge amount of lead there, but perhaps a 10% degradation is seen in 
the front (thin-converter) section.  However, the variation with energy and angle is hard 
to understand.

Hartmut reported on further analysis of the thermal test data, comparing temperature and 
current profiles as a function of time.  He will write it up in the next few days.  High T 
(>30C) runs show current always changing with time, perhaps due to self heating.  He 
has a memo on thermal runaway available on the web.  This shouldn’t be a problem as 
long as heat is removed efficiently from the detectors.  Down to –2C the data agree with 
expections (a 7C change gives a factor of 2 change in current).  At lower T (–14C and -
23C) the temperature drops but current increases.  This is a clear indication of current 
increase from stress.  He would like to discuss with Hytec the strain data at high and low 
temperature.  At high temperature (>50C) there is a glass transition and the adhesive 
flows.  It appears that the analysis of the data did not fully take this into account.

Roberto recounted his AMS experience.  The AMS carbon-fiber support structures 
limited CTE expansion differences with respect to the silicon to a few tens of microns.  

Roberto also mentioned that he has found some resources to produce Si detectors at 
CSEM in Switzerland.  This company now has 6-inch wafer capability.  He would like to 
start a batch using the GLAST design.  Michela sent specs to Roberto.  Hartmut pointed 
out that this document is still evolving, and Roberto should be sure to use the latest 
version.  Roberto would like Hartmut to send him an email with recommendations.  
Perugia will handle this work, including testing.

Action Items
1. Gwelen: find prices for plasma cleaning of hybrid circuits.
2. Gwelen: temperature ramping test of the thermal-test baseplate assembly.
3. John: complete a preliminary design of the adhesive dipping fixture and send to 
Gwelen and Alec for review.
4. Hartmut: write up a report on the analysis of thermal test data.
5. Hartmut: send recommendations on SSD prototyping to Roberto.