The glast VME-IO module was designed and build by SLAC. It is used to test the GLAST tracker controller chip, front-end chip and the MCM's.
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The figure on the right side shows a simplified view of the i/o board. It has two fifos. An output fifo, (also called read-fifo or command fifo) that is used to sent bit patterns to a test board. The second fifo is the input fifo. It reads the data that are comming from a test board. Each fifo has 18 channels. Channel 0 for the output fifo is special |
| address | A32/D32 |
| base address | 0x80000000 |
| address range | 0x10 |
| switch | 1-2-3-4-5-6-7-8 |
|---|---|
| SW1 | 0-1-1-1-1-1-1-1 |
| SW2 | 1-1-1-1-1-1-1-1 |
The glast vme-I/O module has two FIFO's. The output Fifo (oFIFO) is used to send bit patterns to an external module. The input FIFO (iFIFO) reads data from an external module.
For the output FIFO the timing between the clock and an output channel is fixed, except for channel 0. The delay of channel 0 is done by setting bits 0-5 in the control register. The step size is about 1 ns.
There are two timing controlls for the input FIFO.
| Bits | Function | R/W | Default |
|---|---|---|---|
| 31 | Start acquisition 0->1 Transition start acquisition |
RW | 0 |
| 30 | Select source of start of acquisition, 0 - bit 31 start acquisition, 1 - external signal start acquisition |
RW | 0 |
| 29 | Enable clock to Channel 0 |
RW | 0 |
| 28-24 | Unused |
RW | 0 |
| 23-16 | Delay of write command |
RW | 0 |
| 15 | Write FIFO Partial reset (0 - reset), reset data, no conf. |
RW | 0 |
| 14 | Write FIFO Master reset (0 - reset), reset data & conf. |
RW | 0 |
| 13 | Read FIFO Partial reset (0 - reset), reset data, no conf. |
RW | 0 |
| 12 | Read FIFO Master reset (0 - reset), reset data & conf. |
RW | 0 |
| 11-6 | Read-back clk delay in Nns steps. Maximum delay is |
RW | 0 |
| 5-0 | Channel 0 delay in Nns steps. Maximum delay is |
RW | 0 |
Transmit of data will not start unless record (write) FIFO is not empty up to PAE flag.
Each data tacking will fill record FIFO up to Full flag.
Playback will play data until read FIFO is empty.
Last read data will stay on output bus until new playback overwrite it.
Programmable flags configured to 511 words away from empty or full.
FIFO should be out of reset in order to have normal operation (bits 15-12)
Status register:
|
Bits |
Function |
R/W |
Default |
|
31-17 |
Unused |
R |
X |
|
16 |
System in run state - current value |
R |
0 |
|
15 |
Read FIFO programmable Almost Empty Flag - latched value |
RW |
0 |
|
14 |
Read FIFO programmable Almost Full Flag - latched value |
R(W -1 reset) |
0 |
|
13 |
Read FIFO Empty Flag - latched value |
R(W -1 reset) |
0 |
|
12 |
Read FIFO Full Flag - latched value |
R(W -1 reset) |
0 |
|
11 |
Write FIFO programmable Almost Empty Flag - latched value |
R(W -1 reset) |
0 |
|
10 |
Write FIFO programmable Almost Full Flag - latched value |
R(W -1 reset) |
0 |
|
9 |
Write FIFO Empty Flag - latched value |
R(W -1 reset) |
0 |
|
8 |
Write FIFO Full Flag - latched value |
R(W -1 reset) |
0 |
|
7 |
Read FIFO programmable Almost Empty Flag - current value |
R |
0 |
|
6 |
Read FIFO programmable Almost Full Flag - current value |
R |
0 |
|
5 |
Read FIFO Empty Flag - current value |
R |
0 |
|
4 |
Read FIFO Full Flag - current value |
R |
0 |
|
3 |
Write FIFO programmable Almost Empty Flag - current value |
R |
0 |
|
2 |
Write FIFO programmable Almost Full Flag - current value |
R |
0 |
|
1 |
Write FIFO Empty Flag - current value |
R |
0 |
|
0 |
Write FIFO Full Flag - current value |
R |
0 |
Read FIFO register:
|
Bits |
Function |
R/W |
Default |
|
31-18 |
N/A |
- |
0 |
|
17-0 |
Data |
RW |
0 |
Write FIFO flags register:
|
Bits |
Function |
R/W |
Default |
|
31-18 |
N/A |
- |
0 |
|
17-0 |
Data |
RW |
0 |