This page was created November 10, 1995, last modified June 29, 1996
- List of Modules
- Front-End-Readout Chips
The following list provides a brief description of the test modules
that have been build so far.
The Frontend readout is divided into a analog/comparator part and the digitial
part for storing the hit information and comunicate to the dsp daq.
Most of the detector modules were build using the CAFE and LBIC analog chips,
the CDP128, which is a digital pipeline and the HAC chip for the communication
to the DSP-DAQ.
A module with a DDR2 digital chip was build. The DDR2 replaced the CDP128 and
- CAFE (AT&T)
- The CAFE chip is developed at LBNL. It should be used for the ATLAS SVT.
- The LBIC is an bipolar 64 channel analog chip which was developed at UCSC.
- CDP128 + HAC
- The CDP128 is a 128 channel 64 cell deep digital pipeline. For every clock cycle
(typically 40MHz) the binary out put of the amplifier is stored in the pipeline.
It also contains the control logic to communicate with the daq. The HAC chip is
an interface between the CDP128 (1 or many) and the DSP-daq.
- The DDR2 is a sparse readout developed at Oxford. Unlike the CDP128 only the
addresses of the channels that were hitted are stored and send to the daq. The
DDR2 do not uses the HAC because it already contains it functionality.
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