Brief DAQ output format (Qnet2 version2) description and example ================================================================ H.Berns, updated 9/11/03 Revision notes: --------------- This document is valid for the latest Qnet2 firmware versions released after 5/29/2003 with the production of the final version-2 DAQ cards. The data output format has changed significantly from the version-1 firmware, so that PC readout software (e.g. Labview programs) needs to be updated accordingly. The main differences to the older version(s): a) A trigger event can generate multiple data lines, depending on gate width setting and pulse widths. And an input channel can now have multiple hits for each event. b) The hit-tag number (formerly the first column) became obsolete with the new format, so it has been removed. c) The Trigger count number is now full 32 bits instead 28. d) The 8-bit TMC rising edge / falling edge formats have changed. e) The 1PPS count number is now full 32 bits, too, instead 31, which makes direct comparison with the trigger count number easier. See also the following updated user guides provided by our FNAL colleagues, posted on my website in the path http://www.phys.washington.edu/~berns/WALTA/Qnet2/FNAL_files/ : Calculating_Absolute_Time_from_Qnet2_Output.doc QnetCpldII.doc Qnet2UserGuide_Update.pdf TMC_delays_and_gating_explained.doc DAQ output data format (lines not starting with '#' or '*'): ------------------------------------------------------------ - ascii format - each data line contains 16 words - words 1-9 are hex format and described in http://www.phys.washington.edu/~berns/WALTA/Qnet2/FNAL_files/QnetCpldII.doc brief overview: 1: 32-bit trigger count of the 41.66 MHz CPLD clock; range: 00000000...FFFFFFFF; resolution (1 LSB increment) = 24 nsec (*). NOTE: A trigger count of 00000000 means that the DAQ card is still in the initialization phase, i.e. the GPS receiver hasn't started to generate 1PPS pulses yet! Do not use the inital data until the trigger count becomes non-zero! 2: TMC count of rising edge at input 0 (RE0), and trigger-tag; format: bits 0-4 = TMC count of rising edge, resolution = 0.75 nsec (24/32) bit 5 = channel edge tag (1 = valid rising edge, 0 = no risging edge) bit 6 = not used, always 0 bit 7 = trigger tag (1 = new trigger, start of a new event, 0 = follow-up data of a trigger event) 3: TMC count of falling edge at input 0 (FE0); format: bits 0-4 = TMC count of falling edge; bit 5 = channel edge tag (1 = valid falling edge, 0 = no falling edge) bits 6-7 = not used, always 0. 4: TMC count of rising edge at input 1 (RE1); same format as RE0, except bit 7 is always 0. 5: TMC count of falling edge at input 1 (FE1); same format as FE0. 6: TMC count of rising edge at input 2 (RE2); same format as RE1. 7: TMC count of falling edge at input 2 (FE2); same format as FE1. 8: TMC count of rising edge at input 3 (RE3); same format as RE1. 9: TMC count of falling edge at input 3 (FE3); same format as FE1. - word 10: 32-bit CPLD count of the most recent 1PPS time mark (1-pulse-per-second) of the GPS receiver; hex format, range: 00000000...FFFFFFFF, resolution = 24 nsec (*) - word 11: UTC time of most recent GPS receiver data update; 1 per second (unfortunately asynchrounous of 1PPS pulse); format: HHMMSS.mmm where: HH= hour [00...23], MM= minute [00...59], SS= second [00...59], mmm= millisecond [000...999] - word 12: UTC date of most recent GPS receiver data update; format: ddmmyy where: dd= day of month [01...31], mm= month [01...12], yy= year 2-digit format [00...99, e.g. 03=2003] - word 13: GPS valid/invalid flag; format: A= valid (GPS data ok), V= invalid (insufficient satellite lock for 3-D positioning, or GPS receiver is in init phase). Time data might be ok if number of GPS satellites is 3 or more and previous GPS status was "A" (valid) within the last minute. - word 14: number of GPS stallites tracked for time&position solution [decimal: 00...12] - word 15: DAQ status flag (hex): bit0: 0=ok, 1= 1PPS interrupt pending (warning flag: if DAQ card is busy, then 1PPS count might lag behind or get mismatched) bit1: 0=ok, 1= trigger interrupt pending (possibly high trigger rate; if continues, then data might be corrupted) bit2: 0=ok, 1= GPS data possibly corrupted while DAQ uC was/is busy bit3: 0=ok, 1= current or last 1PPS rate is not within 41666666 +/-50 CPLD clock ticks (GPS glitch *or* DAQ uC busy *or* CPLD oscillator not tuned correctly). - word 16: time delay [milliseconds] between 1PPS pulse and GPS data interrupt; a positive number means 1PPS pulse is ahead of GPS data, and negative number means GPS data is ahead of 1PPS pulse by milliseconds. Usage: round (word11 + word16/1000) to nearest full second gives the actual GPS time at last 1PPS pulse (*): 24.00 nsec if the CPLD clock is exactly 41666666.67 Hz. The actual CPLD frequency of each card is usually tuned within +/-30 Hz of the target frequency of 41666667 Hz. Generally, N Hz drift from the target CPLD frequency result in accuracy errors of up to N*24 nsec. E.g. a 30 Hz drift means that the accuracy time error has a range of +/-720 nsec if exactly 24.00 nsec are assumed for a CPLD clock tick time. Probably an error within +/-1000 nsec is acceptable for a school network if the schools are more than 1 mile apart from each other. The CPLD clock frequency fluctuates slightly over time, depending on temperature changes and oscillator ageing drifts. Therefore, in order to achieve high accuracy (+/-50 nsec) in computing the absolute trigger times, the user needs to poll the current CPLD frequency at a regular basis (say once every 5 minutes) with command DG (Display GPS data). If the event rate is high enough (at least 1 event per 100 seconds) then the CPLD frequency can be computed from the 1PPS counter numbers of consecutive events. Example event: -------------- 80EE0049 80 01 00 01 38 01 3C 01 7EB7491F 202133.242 080803 A 04 2 -0389 80EE004A 24 3D 25 01 00 01 00 01 7EB7491F 202133.242 080803 A 04 2 -0389 80EE004B 21 01 00 23 00 01 00 01 7EB7491F 202133.242 080803 A 04 2 -0389 80EE004C 01 2A 00 01 00 01 00 01 7EB7491F 202133.242 080803 A 04 2 -0389 80EE004D 00 01 00 01 00 39 32 2F 81331170 202133.242 080803 A 04 2 +0610 - 5 data lines for one event: the first line has a trigger tag in the RE0 number (2nd number >= 80), followed by 4 lines without trigger tag (2nd number < 80). - GPS date is the same in all 5 lines: 080803 => August 8, 2003 - GPS status: A = valid. - GPS satellites tracked: 04 = 4 satellites. - DAQ status flag = "2" in all 5 lines: bit0=0: no 1PPS pulse pending bit1=1: trigger interrupt pending = data in TMC not empty (possible high rate if bit1 not 0 at end of event) bit2=0: GPS data ok bit3=0: CPLD frequency ok - 1PPS count in lines 1-4 = 0x7EB7491F 1PPS count in line 5 = 0x81331170 => difference = 0x027BC851 => momentary CPLD freqency = 41666641 Hz => 1 CPLD cycle = 1/41666641 sec = 24.000014784 nsec - GPS time of the 1PPS pulse in lines 1-4: round(202133.242 - 0.389) = 20:21:33 UTC GPS time of the 1PPS pules in line 5: round(202133.242 + 0.610) = 20:21:34 UTC - trigger count in line 1 = 0x80EE0049 => difference from 1PPS count: 0x80EE0049-0x7EB7491F = 37140266 (decimal) => time since last 1PPS pulse: 37140266 * 24 nsec = 0.891366384 seconds (assuming CPLD frequency is 41666667 Hz!) => absolute trigger time of this event = 8/8/2003 20:21:33.891366384 --------------------------- (*) computing the corrected absolute time by using the actual CPLD frequency of 41666641 Hz (from consecutive 1PPS counts, see above): => time since last 1PPS pulse: 37140266 / 41666641 = 0.891366933 seconds => absolute trigger time of this event = 8/8/2003 20:21:33.891366933 =========================== -> assuming exact 24.00 nsec CPLD tick would result in a 549 nsec error in this example. - rising and falling edge data of the 4 inputs (RE0...FE3): - line 1: "80EE0049 80 01 00 01 38 01 3C 01": trigger count: 0x80EE0049 = 2163081289 (decimal) RE0: 80 => bit7=1: trigger flag for this event; bit5=0: input 0 has no rising edge. FE0: 01 => input 0 has no falling edge (bit5=0, so ignore bits0-4). RE1: 00 => input 1 has no rising edge. FE1: 01 => input 1 has no falling edge. RE2: 38 => bit5=1: input 2 rising edge (bits0-4)= 0x18 => 24/32 * 24 nsec = 18.0 nsec. FE2: 01 => input 2 has no falling edge. RE3: 3C => bit5=1: input 3 rising edge = 0x1C => 18/32 * 24 nsec = 21.0 nsec. FE4: 01 => input 3 has no falling edge. - line 2: "80EE004A 24 3D 25 01 00 01 00 01": trigger count: 0x80EE004A = 2163081290 (decimal) => +24 nsec from trigger count at event start (line 1). RE0: 24 => input 0 rising edge = 0x04 => 3.00 +24 = 27.00 nsec. FE0: 3D => input 0 falling edge = 0x1D => 21.75 +24 = 45.75 nsec. RE1: 25 => input 1 rising edge = 0x05 => 3.75 +24 = 27.75 nsec. FE1: 01 => input 1 has no falling edge. RE2: 00 => input 2 has no rising edge. FE2: 01 => input 2 has no falling edge. RE3: 00 => input 3 has no rising edge. FE3: 01 => input 3 has no falling edge. - line 3: "80EE004B 21 01 00 23 00 01 00 01": trigger count: 0x80EE004B = 2163081291 (decimal) => +48 nsec from trigger count at event start (line 1). RE0: 21 => input 0 rising edge = 0x01 => 0.75 +48 = 48.75 nsec. FE0: 01 => input 0 has no falling edge. RE1: 00 => input 1 has no rising edge. FE1: 23 => input 1 falling edge = 0x03 => 2.25 +48 = 50.25 nsec. RE2: 00 => input 2 has no rising edge. FE2: 01 => input 2 has no falling edge. RE3: 00 => input 3 has no rising edge. FE3: 01 => input 3 has no falling edge. - line 4: "80EE004C 01 2A 00 01 00 01 00 01": trigger count: 0x80EE004C = 2163081292 (decimal) => +72 nsec from trigger count at event start (line 1). RE0: 01 => input 0 has no rising edge. FE0: 2A => input 0 falling edge = 0x0A => 7.50 +72 = 79.50 nsec. RE1: 00 => input 1 has no rising edge. FE1: 01 => input 1 has no falling edge. RE2: 00 => input 2 has no rising edge. FE2: 01 => input 2 has no falling edge. RE3: 00 => input 3 has no rising edge. FE3: 01 => input 3 has no falling edge. - line 5: "80EE004D 00 01 00 01 00 39 32 2F": trigger count: 0x80EE004D = 2163081293 (decimal) => +96 nsec from trigger count at event start (line 1). RE0: 00 => input 0 has no rising edge. FE0: 01 => input 0 has no falling edge. RE1: 00 => input 1 has no rising edge. FE1: 01 => input 1 has no falling edge. RE2: 00 => input 2 has no rising edge. FE2: 39 => input 2 falling edge = 0x19 => 18.75 +96 = 114.75 nsec. RE3: 32 => input 3 rising edge = 0x12 => 13.50 +96 = 109.50 nsec. FE3: 2F => input 3 falling edge = 0x0F => 11.25 +96 = 107.25 nsec. => pulse timing diagram of the 4 inputs relative to event start: _________ _______________ 0: _____________| || |____________________ __________ 1: ______________| |___________________________________ _______________________________________________ 2: _________| |___ _________________________________________ _____ 3: ___________| |_| +----+----+----+----+----+----+----+----+----+----+----+----+ nsec: 0 10 20 30 40 50 60 70 80 90 100 110 120 ^ trigger