GLAST, the Gamma-ray Large Area Space Telescope, requires about a million channels of low-noise amplifiers in order to read incoming signals from the silicon strip detectors. The amplifiers are VLSI CMOS devices. Each relies on a very large Field Effect Transistor (FET) as the primary amplification element. These transistors produce both white noise, uniform across all frequencies), and 1/f noise (primarily low frequency).
Ideally, the noise of a field effect transistor is due to thermal noise in the channel, which induces a noise current in the drain. This is the source of the white noise. Real transistors also exhibit impurities in the channel and imperfections at the gate-channel interface, typically with a distribution of time constants that yield a 1/f noise spectrum. In practice, measured values for excess noise does not rigorously obey mathematical models for either types of noise. The noise contributions vary with the transistor geometry (length & width) and the commercial process used to fabricate the transistor.
These transistors are used in front-end amplifiers, which means they read detector information and eliminate noise before reporting. This front-end method reduces the size of the data stream, and is a crucial part operating a million-channel detector in a remote low-earth orbit. Understanding the noise characteristics of these amplifiers in the context of extensive simulation studies of GLAST detector models allows amplifier designers to set optimum noise thresholds.
The prototype amplifiers used to date were fabricated in the Hewlett-Packard 0.8 micron (smallest feature size) process. That foundry became obsolete and is now shut down. Therefore, some prototyping and testing of new transistors is required.
This project examines transistors made in the AMI 0.5 micron process. Transistors were designed and fabricated with 3 different channel lengths: 0.9, 1.2, and 0.6 microns. Channel widths were the same for all transistors: 3376.8 ~m.
The objective of this study was to study these transistors, characterizing some performance parameters crucial to designing, and then understanding the datareporting behavior of the GLAST detector.
AMI transistor chips to be tested were wire bonded in 40-pin DIP carriers. DIP carriers were stored in static-free boxes, and handled only with grounding straps.
Evaluated data was imported to Axum software on lab PCs via a custom program using Python software and a GPIB interface.
Noise spectra between 1 e4 and 1 e7 Hz of a typical 0.9,1.2, and 0.6 micron channel length transistor were measured at 4 bias currents: 17, 33, 66, and 132 pA. Supply voltage was held constant at -0.8 VDC. A custom-built amplifier, current meter, voltmeter, power supply, and a Hewlett-Packard 4195A spectrum analyzer were used to measure gain and noise. During noise measurements, the 4145A performed 100 iterations of a 500-point survey across a frequency range between 1 e3 and 1 e8 Hz. Some current and voltage drift always occurred during each measurement cycle, and was corrected for by hand while spectral analysis was paused. In general, supply voltages (nominal - 0.8 VDC) drifted between values of -0.78 and -0.82 before correction. Bias currents drifted in the following range before pausing for adjustment:
17 uA nominal: 15 to 19 uA drift range. 33 uA nominal: 30 to 36 uA drift range. 66 uA nominal: 60 to 72 uA drift range. 132 uA nominal: 125 to 139, uA drift range.
The 100 data iterations were averaged and evaluated by the program on the HP 4145A, and reported to the PC as a single data set.
Noise spectra plots of frequency (Hz) v noise voltage (V/Hz) for each transistor length are presented as figures 1 (Chip 1, 0.9 um), 2 (Chip 1, 1.2 um), and 3 (Chip 1, 0.6 um). A combined noise spectra plot for direct comparison is presented as figure 4. Plots were smoothed with a Lowess curve fitting algorithm available in AXUM.
At all bias currents, the 0.6um transistor demonstrated higher noise values than the other transistors. The 1.2 um demonstrated lower noise values at the 2 lower bias currents, but nearly identical noise values were obtained for the 0.9 and the 1.2 in the frequency range of interest, around 1e6 Hz.
Many measurements needed to be performed repeatedly, because they plotted as many as 3 to 4 orders of magnitude above expected values, which were in the vicinity of 1 V/Hz. A 50-ohm 3-way splitter ring and cables may be responsible: one part of the testing protocol requires that on the three cables be disconnected and left dangling. In some random tests, this cable was left in a position in which its ground shield came in contact with the metal cart on which the spectrum analyzer sat. After some of the magnitude-error data was plotted, and this cable carefully stored in the air when not in use, reasonable results were consistently obtained. I offer no explanation for this phenomenon, but the test equipment did perform better when this adjustment was made.
Gain of 2 examples of each transistor as a function of bias current was measured using a shielded personality test box and a Hewlett-Packard 4145B parameter analyzer.
Plots were made of the 3 transistors of interest on two chips.
Vd, (V, drain voltage) v Id (A, drain current) plots at 5 different Vg's (gate voltage) are presented as figures 5 (Chip 1, 0.9 um), 6 (Chip 1, 1.2 um), 7 (Chip 1, 0.6 um), 8 (Chip 2, 0.9 um), 9 (Chip 2, 1.2, um), and 10 (Chip 2, 0.6 um). To prepare these plots, gate voltages were optimized to provide plots within an Id range between 1 e-7 to 1 e-4. Slopes for each plot at a Vd, of -0.8 VDC were then calculated using a linear slope algorithm against the 40 data points around -0.8 VDC Vd. These slopes are presented in the table below:
0.9 um transistor, Chip 1 Chip 2
gate voltage slope gate voltage slope
-1.25 VDC 1.650e-7 -1.40 VDC 2.6217e-7
-1.30 VDC 7.9167e-7 -1.45 VDC 1.1917e-6
-1.35 VDC 3.5875e-7 -1.50 VDC 4.6408e-6
-1.40 VDC 1.3917e-5 -1.55 VDC 1.5367e-5
-1.45 VDC 4.300e-5 -1.60 VDC 4.0583e-5
1.2um transistor Chip 1 Chip 2
-1.35 VDC 1.3825e-7 same 2.5833e-8
-1.40 VDC 6.6583e-7 gate 1.3000e-7
-1.45 VDC 2.8333e-6 voltages 6.0417e-7
-1.50 VDC 9.0833e-6 2.5417e-6
-1.55 VDC 2.4583e-5 8.4083e-6
0.6 um transistor Chip 1 Chip 2
-0.95 VDC 3.1458e-7 same 3.733e-7
-1.00VDC 1.3734e-6 gate 1.588e-6
-1.05 VDC 5.8033e-6 voltages 6.425e-6
-1.10 VDC 2.1958e-5 2.4167e-5
-1.15 VDC 7.2875e-5 7.6833e-5
Note: different gate voltages were used for the 2 0.9,um transistors to get currents within the 1 e-7 to 1 e-4 range. It was not necessary to set different Vg's for the other transistors.)
1d (A) v Vg (V), with Vd held constant at -0.8 VDC plots were then made for the 3 transistors of interest on two chips. These are presented as figures 11 (Chip 1, 0.9 um), 12 (Chip 1,1.2 gm), 13 (Chip 1, 0.6 gm), 14 (Chip 2, 0.9 um),15 (Chip 2,1.2,um),16 (Chip 2, 0.6 gm), and combined into 1 plot in figure 17.
Transconductance plots of Id/W v gm/Id are presented singly in figures 18, 19, 20, 21, 22, 23, and in figures 24 (0.9 um), 25 (1.2 um), & 26 (0.6 um), with 2 same-length transistors plotted on each page. Figure 27 shows a transconductance plot for all tested transistors on one page.
1 ) Noise Measurements on Radiation-Hardened CMOS Transistors, W. Dabrowski, et
al. (IEEE91) SCIPP 91/24.
2) "Amplifier Noise," Sections 7.11 through 7.20 of Horowitz & Hill, The Art of
Electronics.
3) "Field Effect Transistors, " Chapter 3 of Horowitz & Hill.