These pages summarize the AToM chip tests performed at UCSC.
Last modification 6-12-97.
Here we provide a brief summary of the AToM chip test results. Our main emphasis was testing the digital functionality. However we also study the performance of the analog sections. All digital tests were done at a 16 ns clock (62.5 MHz).
Duty cycle: The radhard chip showed to
be rather sensitive to the clock duty cycle. This sensitivity is due to
the writing of the register which works for a duty cycle of 51% - 61%.
After irradiation, 1 Mrad, the range narrows down to 57% - 60%. The command
decoding, reading register or token passing works in a much wider range
43% - 63% and changes only slightly after the irradiation. These results
are for a clock period of 16 ns (62.5 MHz) and Vdd = 5V.
The duty cycle range depends on the digital voltage (Vdd) and strongly
on the clock period. If the clock frequency is changed from 62.5 MHz to
60 MHz the duty cycle range increases from 3 % to 8 %.
Phase Clock-Command: There is only a narrow range of about 1 ns for the phase between command and clock for which the chip is not working is 2.9 - 3.9 ns. For the radsoft chip the range is a little bit smaller about 0.6 ns.
Power consumption: The power consumption for three radhard chips before and after irradiation was measured. The increase in power after irradiation is less then 2-3 mA per chip.
Details of measurements: