*Please note: Registration for the Tutorial is now closed.
Design Challenges beyond 65nm
Friday, September 15, 9:30 to 12:45, E&MS Building UCSC Campus
Ping Chen, Sr. Staff Application Engineer, Custom IC & Simulation,
Cadence Design Systems
Sravasti Nair, Sr. Staff Application Engineer, Custom IC & Simulation,
Cadence Design Systems
- Advanced Process Nodes Simulation Strategy
- Simulation challenge for advanced process nodes.
- Simulation technology overview
- Reliability simulation
- Aging simulation
- Self-heating simulation
- EMIR Simulation
- Advanced integrated Simulation environment
- Why we need integrated simulation environment?
- Environment for individual block
- Environment for block integration.
- Environment for verification and regression.
- System integration: integrated IC/package/PCB together
- Implementation flow
- Analysis flow
- Advance Node Impact on Physical Design (65 -> 28 -> 16 ->7) and resulting tool support
- New devices (FinFETs) and fluid guardrings
- Double/ Multiple Patterning aka coloring
- Gridded/ track based placement and routing methodology
- In-design dynamic/ post-edit DRC checking to support new constraints including color and grid checks
- Electrically Aware Design Flow
- In-design extraction and analysis of parasitics, EM/ IR and LDE parameters
- Resimulation with parasitics and LDE parameters from a layout in-progress
- Using electrical constraints to verify and meet design requirements
Continuous advancement in process technology following Moore’s law over the past few decades has greatly increased IC design complexity, not just for designers but also for EDA tools. The drive to reduce feature size beyond optical resolution of visible and ultra-violet light has led to multiple masks/ patterns for same layer to allow for a more compact layout. Need for greater scaling and manufacturing accuracy has led to a self-aligned fabrication process requiring gridded, unidirectional interconnects. At the same time, new devices such as tri-gate finFETS have been introduced to address power, leakage and variability associated with these processes. In addition to more restrictive and complex design rules for manufacturability and process characteristics, EDA tools need to account for changes in design methodology such as highly gridded placement and routing.
This presentation will cover these tool enhancements and changes to meet the process technology requirements of these nodes, for both devices and interconnects, with focus on physical implementation.
Furthermore, we will talk about simulation technologies to handle special effects introduced by advanced process nodes, such as high transistor speed, high transistors/RC capacities and reliability effects etc. with reasonable speed and performance while maintaining Spice simulation accuracy. We will also discuss about advanced integrated simulation environment targeting for different design phases to meet the tight design window. Finally, we will touch upon the importance of system integration for advance process nodes and bring up the solution for the system integration, which include IC/Package/PCB, from both implementation and analysis point of views.