DAQ Link Card Schematics
for 30 MHz Operation
April 29th, 1998
Top Level
G-Link Block
G-Link Island
Clock Conditioning
ECL-to-TTL Translators
Data Buffers
Finisar and CAN Bus
FPGA Command Decoding
Page 1
,
Page 2
Clock circuitry
Command TTL-to-ECL Registers
Connectors
Page 1
,
Page 2
Note: My version of ghostview has problems with these files, but they print okay.
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